1. Field of the Invention
The present invention relates generally to clock generating circuits, and more specifically, to a method and circuit for generating a clock signal from a reference clock signal in accordance with an ideal frequency ratio.
2. Background of the Invention
Clock generation circuits are used in a wide range of applications in electronic systems. Phase-lock loop (PLL) clock generators are frequently used and have frequencies typically rationally related to a stable clock frequency by using a feedback divider and a pre-scaling divider. With such a scheme, a PLL can generate a frequency that can be greater or less than the stable clock frequency, and with a rational relationship such as M/N·FR where N is the pre-scaling division factor and M is the feedback divider factor. Such rational frequency multiplying PLLs are frequently used in audio/video (A/V) synchronization circuits, communications circuits and processor clock generation circuits, as well as other applications in which a generated clock signal is required that is synchronized to a timing reference, but the frequency relationship between an available stable clock and the generated clock is not such that simple division can be employed.
Theoretically, any clock frequency can be generated from an arbitrary stable clock frequency and synchronized to a timing reference by such a scheme, as long as the resolution of the pre-scaling divider and feedback divider can be made very large. However, there are practical limitations to using very large dividers. The loop gain of the PLL is inversely proportional to the division factor in the feedback loop, so for large dividers (counters) the loop gain is compromised. Further, for non-terminating rational frequency relationships between the stable clock and the timing reference, increasing the size of the divider chains can reduce the error in the frequency ratio, but never completely eliminate progressive phase differences due to the frequency ratio error. For A/V systems, small errors in a generated synchronization clock can be critical, as relatively long program lengths processed by systems that require relatively high generated clock frequencies lead to phase slip over the length of the program if close tolerances are not held on the generated clock frequency.
For the above reasons, multiple stable clock oscillators are frequently required in A/V synchronization systems, as well as communications systems. Due to differing standards, all required generated clock frequencies that might be supported by a system are not typically related to the stable clock frequency by simple ratios. As an example, the commonly-used 44.1 kilo-samples per second (ksps) CD-Audio rate and its multiple 88.2 ksps do not simply relate to the typical professional audio rates of 32 ksps, 48 ksps, 96 ksps, and 192 ksps. Therefore, typical digital audio systems select between two or more high-frequency stable clock oscillators to generate a clock synchronized to an audio timing reference, depending on whether the data source and timing reference are synchronized to a multiple of 44.1 ksps or 16 ksps.
Further, in some systems, it is desirable to generate a clock signal from another clock signal according to a rational relationship, but without synchronizing the clock signal to a timing reference. For example, in the above-described audio systems, when a timing reference is not present, it is still generally desirable to generate a clock according to a rational relationship to the stable clock. Therefore, in audio systems that still require generation of, for example, 44.1 ksps-based clock rates vs. 16 ksps-based clock rates, two oscillators are still required. For example, when supporting sampling of an analog audio source with no external timing reference, the sampling device must generally provide a sampling clock generated in conformity with a multiple of one of 44.1 ksps and 16 ksps.
Therefore, it would be desirable to provide a method and circuit for maintaining an ideal ratio between a rationally controlled frequency source and a timing reference so a stable clock can be produced with a more exact frequency relationship between the stable clock and a generated clock that is synchronized to a timing reference. It would further be desirable to generate a clock signal that is rationally related by an ideal ratio from a stable clock signal without synchronization to a timing reference other than the stable clock signal itself.